Task 4.2: Technological limitations of fractal-shaped devices

• Deliverables: D10 T4.2 Final Task Report
• Outputs: Assessment of the viability of the designs to be prototyped in task 4.3.

Before going into the manufacturing of the prototypes it is necessary to assess the resolution that is required in the prototype to exhibit the desired properties. It is also necessary to assess the loss efficiency that will derive from the ohmic losses of the materials involved in the manufacturing of the prototypes. This double assessment will be done numerically by means of the software developed in WP3. Also some specific experiments on basic structures (bare substrates, variable width printed lines…) will be performed to ascertain the validity of numerical predictions.

The task will develop the guidelines, i.e. materials, spatial resolution, necessary to build the prototypes.

The first limitation that we have when working with fractal devices is that they actually are the result of infinite iterations of an IFS or a MRCM. In practice, we always work with structures resulting from a finite number of iterations of these algorithms: the pre-fractals. If highly iterated devices would be needed, technological limitations in the manufacturing procedures would appear.

When manufacturing a pre-fractal device, the width of the curve is the parameter that makes the device attainable (manufacturable) or not. The dimension w will always refer here to the strip width if we are designing microstrip devices, or a wire diameter if we were designing wired devices, ans S to the size of the curve. In any case, we will refer to planar designs, i.e. fractal curves that are included in a plane, the most widely used in the Fractal Electrodynamics literature.

The next figures show the maximum iteration achievable for a given fractal design as a function of the strip width w for the Koch, Hilbert and Sierpinski pre-fractals.

The Kock curve

The technological limitation for the maximum iteration when manufacturing a Koch pre-fractal is connected with the width of the curve. We have stablished the limit between the manufacturability and non-manufacturability region for a given pre-fractal iteration when the width of the curve “fills the gap” of the equilateral triangle side of finest resolution.

In Fig. 53 the area over the curve represents the values that cannot be manufactured with our present technology (i.e. for a given w/S ratio). The area under and on the curve includes the iterations manufacturable with a given w/S ratio. Blue dots are typical w/S values of manufactured structures taken from literature, while red dots are typical w/S values of simulated structures also taken from literature. All of these ratios correspond to monopole antenna designs. We should emphasize from figure 53 that the highest pre-fractal iteration manufactured is the 5^th and that all of these designs referred in literature correspond to ratios w/S around 10^-3 and 10^-2.

Figure 53: Maximum iteration of a manufacturable Koch curve pre-fractal with a given w/S ratio. The region over the curve includes the designs that cannot be fabricated. Red and blue dots show, respectively, the highest iterations simulated and manufactured for monopole antenna designs taken from literature.

The Hilbert curve

The maximum manufacturable Hilbert pre-fractal iteration for a given w/S is displayed in figure 54. Dots show the Hilbert pre-fractals of highest iterations (simulated and manufactured) whose dimensions are taken from literature.

Figure 54: Maximum iteration of a manufacturable Hilbert curve pre-fractal with a given w/S ratio. The region over the curve includes the designs that cannot be fabricated. Red and blue dots show, respectively, the highest iterations simulated and manufactured for monopole antennas. These values are taken from literature.

The Sierpinski curve

The maximum manufacturable Sierpinski pre-fractal iteration N versus the technological resolution w/S is shown in figure 11. The highest iterations (simulated and measured) found in literature are also displayed in the figure.

Figure 55: Maximum iteration of a manufacturable Sierpinski curve pre-fractal with a given w/S ratio. The region over the curve includes the designs that cannot be fabricated. Red and blue circles show, respectively, the highest iterations found in literature that have been simulated and manufactured.

Limitations in the manufacturing procedures at UPC

Figures 53, 54 and 55, are very useful to find the number of iterations that would be manufacturable, given a certain resolution (w/S) in our fabrication procedures.

At UPC the standard procedures for manufacturing printed circuit boards allow the fabrication of strips as small as 100 μm on CuClad substrate (etching, 35 μm), 80 μm on Rogers substrate (etching, 17.5 μm), or 20 μm on a superconductor (etching, 200 μm).

For instance, figure 53 reveals that for a Koch pre-fractal monopole with a resonant frequency around 1-2 GHz, the maximum attainable iteration is the 6^th.